Nasdaq

ACM Research Highlights Availability of Portfolio of Wafer-Level Packaging Processing Equipment for OSAT Customers

Extensive Array of Back-End and Advanced Packaging Wet Wafer Process Equipment Leverages ACM’s Experience to Address Emerging Requirements for Wafer-Level Packaging FREMONT, Calif., Oct. 15, 2020 ...
Nasdaq

ACM Research Launches Its First Plating Tool to Support Wafer-Level Packaging and Plating Applications in Compound Semiconductor Manufacturing

FREMONT, Calif., Aug. 25, 2021 (GLOBE NEWSWIRE) -- ACM Research, Inc. (ACM) (NASDAQ: ACMR), a leading supplier of wafer processing solutions for semiconductor and advanced wafer-level packaging (WLP) ...
EDN

Collision Course At The Wafer Level?

San Francisco —Competing industry teams are racing to develop wafer-level packaging (WLP) as front- and backend semiconductor manufacturing and assembly technologies converge in the advanced packaging ...
EDN

STATS expands wafer-level packaging output

SAN JOSE, Calif. — Citing renewed demand, Singapore's STATS ChipPAC Ltd. is expanding its capacity for wafer-level packaging. STATS ChipPAC has been on a production ramp with wafer-level packaging ...
Seeking Alpha

ACM Research Expands Advanced Packaging Portfolio with Introduction of Frame Wafer Cleaning Tool

FREMONT, Calif., May 08, 2024 (GLOBE NEWSWIRE) -- ACM Research, Inc. (ACMR) (“ACM”) (NASDAQ: ACMR), a leading supplier of wafer processing solutions for semiconductor and advanced wafer-level ...
Seeking Alpha

ACM Research Receives Orders for Wafer-Level Packaging Tools from U.S. Customer and R&D Center

FREMONT, Calif., Sept. 04, 2024 (GLOBE NEWSWIRE) -- ACM Research, Inc. (ACMR) (“ACM”) (NASDAQ: ACMR), a leading supplier of wafer processing solutions for semiconductor and advanced wafer-level ...
Digi Times

Samsung steps up fan-out wafer-level packaging deployment

Samsung Electronics has stepped up its deployment in the fan-out (FO) wafer-level packaging segment with plans to set up related production lines in Japan, according to industry sources. Samsung has ...
Semiconductor Engineering

One Micron Damascene Redistribution for Fan-Out Wafer Level Packaging Using a Photosensitive Dielectric Material

This study investigates creation of 1.0µm RDL structures by a damascene process utilizing a photosensitive permanent dielectric material. The advantage of the photosensitive dielectric approach is ...
Business Wire

Nordson MARCH to Present Paper on Plasma Applications for Wafer-Level Packaging at ICEPT

CONCORD, Calif.--(BUSINESS WIRE)--Nordson MARCH, a division of Nordson (NASDAQ:NDSN), a global leader in plasma processing technology, will present the paper, "Plasma Applications for Wafer Level ...
Digi Times

South Korea initiates major R&D project to boost chips packaging competitiveness

Recognizing the strategic importance of semiconductor packaging technology, the South Korean government is reportedly initiating a major packaging technology R&D project aimed at assisting companies ...
Electronic Design

Chip Packaging Part 6 - Wafer to Panel Level Packaging

Dr. Navid Asadi’s group takes a look at wafer to panel level chip packaging. This is the six of a mutlipart series on chip packaging technologies. Navid Asadi is an assistant professor in the ...
Semiconductor Engineering

Next Steps For Panel-Level Packaging

Tanja Braun, group manager at Fraunhofer Institute for Reliability and Microintegration (IZM), sat down with Semiconductor Engineering to talk about III-V device packaging, chiplets, fan-out and panel ...